Contactless nor-type memory array and its fabrication Methods

ABSTRACT

A contactless NOR-type memory array of the present invention comprises a plurality of integrated floating-gate layers formed on a shallow-trench isolation structure, a plurality of word lines having an interlayer dielectric layer formed on an elongated control-gate layer for each word line, a plurality of common-source bus lines having a silicided conductive layer formed over a flat bed for each common-source line and, a plurality of bit lines with each bit line being integrated with a plurality of silicided conductive islands formed on the common-drain diffusion regions. The contactless NOR-type memory array of the present invention may offer: a cell size of 4F 2 , no contact problems for shallow source/drain junction of the cell, lower common-source bus line resistance and capacitance, and better density*speed*power product as compared to existing NAND-type memory array.

FIELD OF THE INVENTION

[0001] The present invention is related generally to a non-volatilesemiconductor memory array and its fabrication methods, and moreparticularly, to a contactless NOR-type non-volatile semiconductormemory array and its fabrication methods for high-density mass storageapplications.

DESCRIPTION OF THE RELATED ART

[0002] A semiconductor memory is in general organized in a matrix formhaving a plurality of rows perpendicular to a plurality of columns. Theintersection of one row and one column has a storage element called amemory cell and each memory cell is capable of storing a binary bit ofdata. Each of the plurality of rows represents a word line and each ofthe plurality of columns represents a bit line. A decoder systemincluding a row decoder block and a column decoder block is used togenerate the binary-coded input in order to select the desired row orcolumn for a write or read operation. Basically, the speed*power*densityproduct is a figure of merits for evaluating the performance of asemiconductor memory. In general, the cell size is a major concern forhigh-density mass storage applications; the RC delay time of the wordline and the bit line is a major concern for high-speed write or readoperation; and the operation current and voltage during a write or aread is a major concern for operation power.

[0003] A flash memory is in general organized in a NAND-typeconfiguration or a NOR-type configuration. A NAND-type flash arrayhaving a byte of cells formed in series with sharing source/draindiffusion regions has a density that is about twice of a NOR-type flasharray. However, the access time is slow for a NAND-type array due to theseries-connected nature of cells and, therefore, a NAND-type array islimited to 16 cells in series in order to avoid excessive seriesresistance. Moreover, a NAND-type array is in general programmed byFowler-Nordheim tunneling between the overlapping area of a draindiffusion region of a cell and its floating gate and the programmingspeed of a NAND-type array is relatively slow as compared thehot-electron injection used often by a NOR-type array. In additions ahigh-voltage is needed to be applied to the word lines of the unselectedcells, the complicated support circuits are required for a NAND array.Therefore, the only advantage of a NAND-type array is the density andthe cell size can be made to be 4F² (2F×2F), where F is theminimum-feature-size of technology used.

[0004] A typical NOR-type array is shown in FIG .1, where FIG. 1A showsa simplified top plan view of a 2×2 array; FIG. 1B shows a schematiccircuit diagram of FIG. 1A; FIG. 1C shows a cross-sectional view alongA-A′ direction in FIG. 1A; and FIG. 1D shows a cross-sectional viewalong B-B′ direction in FIG. 1A. Now, referring to FIG. 1A, the activeregion of a NOR-type array is defined and formed on a p-semiconductorsubstrate 10 and the isolation region (outside of the active region) isformed with a thicker field-oxide layer (FOX), in which a larger activeregion is defined for forming a contact. A thin tunneling-oxide layer isformed over the active region, then a floating-gate (FE) made of dopedpolycrystalline silicon is formed over the thin tunneling-oxide layerand the field-oxides (FOX) and is patterned to have a portion remainedon the field-oxides to increase the coupling ratio of the floating-gate,as shown in FIG. 1D. An intergate dielectric layer of theoxide-nitride-oxide (ONO) structure is formed over the patternedfloating-gate layer and the field-oxides, then a control-gate (CG) layeris formed over the intergate dielectric layer and is patterned to formthe word lines (WL) and the stack-gate regions of the cells, as shown inFIG. 1A and FIG. 1C. The no source/drain diffusion regions are formed ina self-aligned manner in the semiconductor substrate 10 by using thepatterned word lines as an implantation mask, as shown in FIG. 1C. Atick interlayer dielectric layer made of oxide is formed over thestructure and is planarized, then the contact holes are open and filledwith the metal plugs, as shown FIG. 1C. A metal film is deposited overthe planarized structure and is then patterned to form the bit lines(BL) perpendicular to the word lines, as shown in FIG. 1A and FIG. 1C,in which each of the bit lines is electrically connected to the draindiffusion regions of the cells in a column through the contact holesbeing filled with the metal plugs. As shown in FIG. 1A, the unit cellarea as marked by the dash line is at least 8F² if the space between thecontact and the word line is F. It is quite clear that the contact in acell of a NOR-type array becomes a major obstacle for reducing the cellsize.

[0005] It is therefore an objective of the present invention to providea contactless NOR-type non-volatile memory array with a much reducedcell size.

[0006] It is another objective of the present invention to providemethods of making a contactless NOR-type non-volatile memory array witha cell size of 4F².

SUMMARY OF THE INVENTION

[0007] A contactless NOR-type memory array and its fabrication methodsare disclosed by the present invention. A contactless NOR-type memoryarray comprises: a plurality of parallel isolation regions being formedalternately on a semiconductor substrate of a first conductivity typewith a plurality of active regions formed therebetween, wherein in araised field-oxide film is formed on each of the plurality of parallelisolation regions and a thin tunneling-dielectric layer is formed oneach of the plurality of active region; a plurality of word lines beingformed alternately and transversely to the plurality of parallelisolation regions, wherein each of the plurality of word lines comprisesan elongated control-gate layer being sandwiched between an interlayerdielectric layer formed on the top and an intergate dielectric layerformed at the bottom, and a plurality of integrated floating-gate layersbeing formed beneath the intergate dielectric layer, wherein each of theplurality of integrated floating-gate layers comprises a majorfloating-gate layer being formed on the thin tunneling-dielectric layerand two extended floating-gate layers being formed separately on aportion of each of two nearby raised field-oxide films; a plurality ofcommon-source diffusion regions being formed along the common-sourcelines and a plurality of common-drain diffusion regions being formedalong the common-drain lines; a plurality of dielectric spacers beingformed over the sidewalls of each of the plurality of word lines,wherein the raised field-oxide films along each of the common-sourcelines are etched to set up a flat bed formed alternately by thecommon-source diffusion regions and the etched field-oxide films; asilicided common-source conductive layer being formed between a pair ofdielectric spacers and over a flat bed with a second thick-oxide layerformed on the top; a silicided common-drain conductive island beingformed between another pair of dielectric spacers and on each of theplurality of common-drain diffusion regions and a portion of two raisedfield-oxide films formed nearby; and a plurality of bit lines beingformed transversely to the plurality of word lines having each of theplurality of bit lies formed over a flat surface formed alternately bysecond thick-oxide layer, interlayer dielectric layer, and silicidedcommon-drain conductive islands, wherein each of the plurality of bitlines comprises a hard masking layer being formed on a metal layer tosimultaneously pattern and form the metal layer and said silicidedcommon-drain conductive islands along each of the plurality of bitlines.

[0008] The plurality of parallel isolation regions can be formed byusing either shallow-trench-isolation (STI) technique or local-oxidationof silicon (LOCOS) techniques; the elongated control-gate layer ispreferably a composite conductive layer having a refractory-metalsilicide layer formed over a doped polycrystalline-silicon layer; theinterlayer dielectric layer is preferably a composite dielectric layerhaving a capping silicon-nitride layer formed on a first thick-oxidelayer or an insulator layer of low dielectric constant; the intergatedielectric layer is preferably a composite dielectric layer having anoxide-nitride-oxide structure or a nitride-oxide structure; the hardmasking layer comprises a masking dielectric layer and its two sidewalldielectric spacers and is preferably made of silicon nitrides,silicon-oxynitrides or silicon oxides; the integrated floating-gatelayer is preferably made of doped polycrystalline-silicon or dopedamorphous-silicon; the dielectric spacers formed over the sidewalls ofthe plurality of word lines are preferably made of silicon-oxides,silicon-oxynitrides, silicon-nitride, or dielectric materials of lowdielectric constant; the silicided common-source conductive layer andthe silicided common-drain conductive island are preferably arefractory-metal suicide layer formed on a doped polycrystalline-siliconor doped amorphous-silicon layer; the metal layer is preferably made ofaluminum (Al), copper (Cu), tungsten (W), or tungsten-silicide (WSi₂)formed on a barrier-metal layer such as titanium-nitride (TiN) ortantalum-nitride (TaN); the common-source diffusion region is preferablya double-diffused structure having a heavily-doped source diffusionregion of a second conductivity type formed within a lightly-dopedsource diffusion region of the second conductivity type; thecommon-drain diffusion region can be a heavily-doped drain diffusionregion of a second conductivity type or a double-diffused structurehaving a heavily-doped diffusion region of second conductivity typeformed within a lightly-doped diffusion region of either a firstconductivity type or a second conductivity type.

[0009] The contactless NOR-type memory array of the present inventionmay offer the following advantages and features: a cell size of 4F², nocontact problems for shallow source/drain junction, lower common-sourcebus line resistance and capacitance, lower common-source junctionleakage current, and better density speed power product as compared toexisting NAND-type memory array.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1A through FIG. 1D show the schematic diagrams of the priorart, in which FIG. 1A shows a simplified top plan view of a NOR-typeflash memory array; FIG. 1B shows a circuit diagram of a NOR-type flashmemory array; FIG. 1C shows a cross-sectional view along A-A′ in FIG.1A; and FIG. 1D shows a cross-sectional view along B-B′ in FIG. 1A;

[0011]FIG. 2A through FIG. 2F show the schematic diagrams of the presentinvention, in which FIG. 2A shows a top plan view of a contactlessNOR-type flash memory array; FIG. 2B shows a circuit diagram of acontactless NOR-type flash memory array; FIG. 2C shows a cross-sectionalview along A-A′ in FIG. 2A; FIG. 2D shows a cross-sectional view alongB-B′ in FIG. 2A; FIG. 2E shows a cross-sectional view along C-C′ in FIG.2A; and FIG. 2F shows a cross-sectional view along D-D′ in FIG. 2A;

[0012]FIG. 3A through FIG. 3F show the process steps and theircross-sectional views of fabricating a shallow-trench-isolation (STI)structure having the integrated floating-gate structure; and

[0013]FIG. 4A through FIG. 4I show the process steps and theircross-sectional views of fabricating a contactless NOR-type flash memoryarray.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Referring now to FIG. 2A, there is shown a top plan view of acontactless NOR-type flash memory array. A plurality ofshallow-trench-isolation lines (STI lines) are formed alternately in asemiconductor substrate 100 with a plurality of active-region linesformed therebetween. A plurality of word lines (WL0˜WL3) are formedalternately and are perpendicular to the plurality of STI lines, inwhich a plurality of integrated floating-gate layers (IFG) are formedbeneath an elongated control-gate layer (CG) being acted as a word line.Each of the plurality of integrated floating-gate layers has a majorfloating-gate layer formed over a thin tunneling dielectric layer in alactive-region line and two extended floating-gate layers formedseparately on a portion of each of two field-oxides (FOX) in the nearbySTI lines. An interlayer dielectric layer including a second maskingdielectric layer over a first tick-oxide layer is formed over theelongated control-gate layer. A plurality of common-source bus lines(SL0˜SL2) are formed alternately in every two word lines and each of theplurality of common-source bus lines is formed between two nearby wordlines, in which a silicided fourth conductive layer is formed over aflat bed located between two sidewall dielectric spacers having the flatbed formed alternately by the source diffusion regions and theplanarized field-oxides. A plurality of bit lines (BL0˜BL3) are formedalternately and are perpendicular to the plurality of word lines, inwhich each of the plurality of bit-lines is formed above each of theplurality of active-region lines and is formed on a plurality ofsilicided fourth conductive islands being formed on a plurality ofcommon-drain diffusion regions. As indicated in FIG. 2A, the cell sizeof a contactless NOR-type memory array is 4F², where F is theminimum-feature-size of technology used.

[0015]FIG. 2B shows a circuit diagram of FIG. 2A, where the circlemarked at the intersection point of the lines represents aninterconnection rater than a contact.

[0016] Referring now to FIG. 2C through FIG. 2F, there are shown variouscross-sectional views as indicated in FIG. 2A, in which FIG. 2C shows across-sectional view along A-A′; FIG. 2D shows a cross-sectional viewalong B-B′; FIG. 2E shows a cross-sectional view along C-C′; and FIG. 2Fshows a cross-sectional view along D-D′. As shown in FIG. 2C, a metallayer 117 a acted as a bit line (BL) is formed over a plurality of treeregions, where each of the plurality of three regions includes acommon-source region, a word-line region and a common-drain region. Theword-line region comprises from top to bottom an interlayer dielectriclayer 109 a, a control-gate layer 108 a, and an intergate dielectriclayer 107 a, a major floating-gate layer 102 b, and a thin tunnelingdielectric layer 101 b formed on a semiconductor substrate 100. Thecommon-source region includes two dielectric spacers 113 b being formedover the sidewalls of the word-line regions, and between two dielectricspacers 113 b comprises from top to bottom a first thick-oxide layer 116a, a silicide layer 115 b, a fourth conductive layer 114 b, aheavily-doped (n⁺) source diffusion region 112 b, and a lightly-doped(n⁻) source diffusion region 110 a. The common-drain region includes twodielectric spacers 113 a being formed over the sidewalls of the wordlines, and between two sidewall spacers 113 a comprises from top tobottom a silicide layer 115 a, a fourth conductive layer 114 a, aheavily-doped (n⁺) drain diffusion region 112 a, and a lightly-doped(p⁻) drain diffusion region 111 a. Note that the lightly-doped (p⁻)drain diffusion region 111 a is mainly used to tailor the drain electricfield and further to reduce the punch-through effects of a memory cell.The lightly-doped (p⁻) drain diffusion region 111 a can be deleted orsubstituted by the lightly-doped (n⁻) drain diffusion region, dependingon the programming requirement. The third masking dielectric layer 118 awith its two third dielectric spacers 119 a formed on the bit line 117 ais mainly used to define the bit line width, as will be clearlydescribed later.

[0017]FIG. 2D shows a cross-sectional view along B-B′ in FIG. 2A, whichis a cross-sectional view along a common-source line (SL). As shown inFIG. 2D, a fourth conductive layer 114 b capped with a silicide layer115 b is formed on a flat bed being formed alternately by the planarizedfield-oxides (FOX) 104 c and the heavily-doped (n⁺) source diffusionregions 112 b. A first thick-oxide layer 116 a is formed over thesilicide layer 115 b and the bit lines 117 a are formed above theactive-region lines. The width of a bit line is defined by a thirdmasking dielectric layer 118 a and its two third dielectric spacers 119a formed over the sidewalls of the third masking dielectric layer 118 a,and therefore, the width of a bit line is wider than a minimum-featuresize (F) and the space of the bit lines can be made to be smaller than aminimum-feature-size (F) for a minimum metal pitch of 2F. It is clearlyseen that the common-source bus line of a contactless NOR-type memoryarray will give lower bus-line resistance, lower bus-line capacitance,and lower junction leakage current as compared to those of the n+ buriedcommon-source line of the prior art.

[0018]FIG. 2E shows a cross-sectional view along C-C′ in FIG. 2A, whichis a cross-sectional view along a word line. As shown in FIG. 2E, aplurality of integrated floating-gate layers are formed along a wordline and each of the plurality of integrated floating-gate layersincludes a major floating-gate layer 102 b formed on a thin tunnelingdielectric layer 101 b and two extended floating-gate layers 105 dformed separately on a portion of each of two nearby field-oxides (FOX)104 b. An intergate dielectric layer 107 a is formed over the pluralityof integrated floating-gate layers and the field-oxides 104 b; theelongated control-gate layer 108 a is formed over the intergatedielectric layer 107 a; and an interlayer dielectric layer 109 a isformed over the elongated control-gate layer 108 a. Similarly, the bitlines 117 a are patterned and formed over the interlayer dielectriclayer 109 a as shown in FIG. 2D.

[0019]FIG. 2F shows a cross-sectional view along D-D′ in FIG. 2A, whichis a cross-sectional view along a common-drain line (DL). As shown inFIG. 2F, a plurality of bit lines 117 a are formed by a hard maskinglayer including a third masking dielectric layer 118 a and its two thirddielectric spacers 119 a, and the fourth conductive layer 114 a cappedwith a silicide layer 115 a are etched down in a self-aligned manner tothe raised field-oxides 104 b. It is clearly seen that the dielectricspacers 119 a are mainly used to eliminate the misalignment ofphotolithography and, therefore, the original contact area between thefourth conductive layer 114 a and the heavily-doped drain diffusionregion 112 a will not be changed It should be noted that the gapsbetween the bit lines can be refilled with planarized CVD oxides beforeor after the third masking dielectric layer 118 a and their sidewallspacers 119 a are removed.

[0020] Based on the above description, the advantages and features ofthe present invention are summarized as follows:

[0021] (a) The contactless NOR-type memory array of the presentinvention can offer much smaller cell size as compared to that of theconventional NOR-type memory array having the bit-line contacts;

[0022] (b) The contactless NOR-type memory array of the presentinvention can offer a minimum cell size of 4F² which is equivalent tothat of the NAND-type memory array;

[0023] (c) The contactless NOR-type memory array of the presentinvention doesn't have the contact problems for a shallow source/drainjunction, therefore the source/drain junction depth in a cell can beeasily scaled down;

[0024] (d) The contactless NOR-type memory array of the presentinvention can offer a common-source bus line with lower bus-lineresistance, lower bus-line capacitance, and lower bus-line junctionleakage current; and

[0025] (e) The contactless NOR-type memory array of the presentinvention offers a much better density*speed*power product and muchsimpler peripheral circuits for write, read and erase as compared to theNAND-type memory array.

[0026] Referring now to FIG. 3A through FIG. 3F, there are shown theprocess steps and their cross-sectional views for forming ashallow-trench-isolation structure having an integrated floating-gatestructure for each of flash memory cell in a flash memory array. Asshown in FIG. 3A, a thin tunneling dielectric layer 101 is formed on asemiconductor substrate 100, a first conductive layer 102 is formed onthe thin tunneling dielectric layer 101, and a first masking dielectriclayer 103 is then formed on the first conductive layer 102. The thintunneling dielectric layer 101 is preferably a thermal-oxide layer or anitrided thermal-oxide layer having a thickness between 60 Å and 150 Å.The first conductive layer 102 is preferably a dopedpolycrystalline-silicon or a doped amorphous-silicon layer having athickness between 1000 Å and 3000 Å and is preferably deposited bylow-pressure chemical-vapor-deposition (LPCVD). The first maskingdielectric layer 103 is preferably a silicon-nitride layer having athickness between 1000 Å and 5000 Å and is preferably deposited byLPCVD. The patterned photoresist PR1 is formed on the first maskingdielectric layer 103 to define a plurality of shallow-trench-isolation(STI) lines with a plurality of active-region lines (covered by PR1)formed therebetween. Note that the minimum-feature-size F can be used todefine the width and the space of the patterned photoresist PR1.

[0027]FIG. 3B shows that the first masking dielectric layer 103, thefirst conductive layer 102, and the thin tunneling dielectric layer 101,which are not covered by PR1, are anisotropically etched and thesemiconductor substrate 100 is anisotropically etched to form aplurality of shallow trenches, and then the patterned photoresist PR1 isstripped. Subsequently, a thick oxide film 104 is deposited by CVD orhigh-density plasma CVD to fill up the etched gaps and the planarizationis performed by chemical-mechanical polishing (CMP) with the firstmasking dielectric layer 103 a as a polishing stop to form theplanarized field-oxides (FOX) 104 a, as shown in FIG. 3B. The depth ofshallow trenches formed in the semiconductor substrate is preferablybetween 3000 Å and 8000 Å.

[0028]FIG. 3C shows that the planarized field-oxides 104 a areanisotropically etched back to a level approximately equal to a halfthickness of the first conductive layer 102 a and the planarized secondconductive layers 105 a are formed over the etched-back gaps. Theplanarized second conductive layer 105 a is first formed by depositing asecond conductive layer 105 to fill-up the etched-back gaps and thenplanarizing the second conductive layer 105 using CMP with the firstmasking dielectric layer 103 a as a polishing stop. The secondconductive layer 105 is preferably a doped polycrystalline-silicon layeror a doped amorphous-silicon layer as deposited by LPCVD.

[0029]FIG. 3D shows that the planarized second conductive layers 105 aare etched back to a level approximately equal to a thickness of thefirst masking dielectric layer 103 a and the first dielectric spacers106 a are formed over the sidewalks of the first masking dielectriclayer 103 a. The first dielectric spacers 106 a are formed by depositinga first dielectric layer 106 and etching back anisotropically thethickness of the first dielectric layer 106. Note that the spacer widthis approximately equal to the thickness of the first dielectric layer106. The first dielectric spacer 106 a is preferably made ofsilicon-nitrides deposited by LPCVD. Using the first dielectric spacers106 a and the first masking dielectric layers 103 a as the etching mask,the etched-back second conductive layers 105 b are anisotropicallyetched to form the extended floating-gate layers 105 c, as shown in FIG.3D.

[0030]FIG. 3E shows that the first masking dielectric layers 103 a andthe first dielectric spacers 106 a are removed preferably byhot-phosphoric acid and an intergate dielectric layer 107 is then formedover the structure. The intergate dielectric layer 107 is preferably acomposite dielectric layer of an oxide-nitride-oxide (ONO) structure ora nitride-oxide structure having an equivalent oxide thickness of about100 Å.

[0031]FIG. 3F shows that the third conductive layer 108 is deposited onthe intergate dielectric layer 107. The third conductive layer 108 ispreferably a composite conductive layer of a tungsten-silicide (WSi₂)layer over a doped polycrystalline-silicon layer. From FIG. 3F, it isclearly seen that the integrated floating-gate layer consisting of amajor floating-gate layer 102 a and two extended floating-gate layers105 c may largely increase the coupling ratio of the floating-gate andthe width of the extended floating-gate layer 105 c can be easilycontrolled by the spacer width without using the extra maskingphotoresist steps. Moreover, the surface of the third conductive layer108 is rather flat for fine-line lithography.

[0032] Referring now to FIG. 4A through FIG. 4I, there are shown theprocess steps and their cross-sectional views along A-A′ shown in FIG.2A for fabricating a contactless NOR memory array based on the isolationstructure shown in FIG. 3F. As shown in FIG. 4A, an interlayerdielectric layer 109 is formed over the third conductive layer 108 asshown in FIG. 3F. The interlayer dielectric layer 109 is preferably asecond masking dielectric layer formed over a first thick-oxidelayer(not shown). The second making dielectric layer is preferably asilicon-nitride layer having a thickness between 200 Å and 1000 Å, asdeposited by LPCVD. The first thick-oxide layer is preferably depositedby LPCVD and its thickness is between 2000 Å and 5000 Å. The patternedphotoresist PR2 is formed over the interlayer dielectric layer 109 todefine the word lines (under PR2) and the common-source/drain diffusionregions (between PR2). It should be noted that the width and the spaceof PR2 can be defined to be the minimum feature size (F) as shown inFIG. 4A.

[0033]FIG. 4B shows that the interlayer dielectric layer 109, the thirdconductive layer 108, and the intergate dielectric layer 107 areanisotropically etched, the extended floating-gate layer 105 c (as shownin FIG. 3F) is removed, and the major floating-gate layer 102 a ispartially etched. The patterned photoresist PR3 are formed over thecommon-drain lines and the part of the interlayer dielectric layers 109a as shown in FIG. 4B, in which the common-source lines are not coveredby PR3. Ion implantation can be performed by implanting phosphorous ions(P³¹) across the remained major floating-gate layer 102 c and the thintunneling dielectric layer 101 a into the semiconductor substrate 100 ina self-aligned manner to form the lightly-doped source diffusion regions110 a and, subsequently, the planarized field-oxides 104 b (shown inFIG. 3F) along the common-source lines are etched back to a levelslightly higher the top level of the thin tunneling-dielectric layer 101a in order to form a flat bed later,

[0034]FIG. 4C shows that the patterned photoresist PR3 are stripped, theremained major floating-gate layers 102 c over the common-source/drainlines are selectively removed, and then a patterned photoresist PR4 areformed over the common-source lines and the part of the interlayerdielectric layers 109 a to expose the common-drain lines. Ionimplantation is performed by implanting boron ions (B¹¹) across the thintunneling dielectric layer 101 a into the semiconductor substrate 100 toform p-diffusion regions 111 a for the common-drain diffusion regions.It should be noted that the p-diffusion region formed in thecommon-drain diffusion regions may enhance the lateral electric fieldnear the drain edge to improve the hot-electron-injection efficiency forprogramming and may also increase the punch-through voltage of thestack-gate cells. If the p-diffusion regions 111 a are not required, thepatterned photoresist PR4 can be omitted.

[0035]FIG. 4D shows that the patterned photoresist PR4 are stripped andion-implantation is performed by implanting arsenic ions (AS⁷⁵) acrossthe thin tunneling dielectric layers 101 a into the common-sourcediffusion regions to form the heavily-doped n+ source-diffusion regions112 b and the common-drain diffusion regions to form the heavily-dopedn⁺ drain-diffusion regions 112 a. Similarly, if the p-diffusion regionin the common-drain diffusion regions is removed (PR4 is omitted), thecommon-drain diffusion region becomes a heavily-doped n⁺ drain diffusionregion.

[0036]FIG. 4E shows that the thin tunneling dielectric layers 101 a overthe common-source/drain diffusion regions 112 a, 112 b are removed by adip etching in a dilute hydrofluoric acid and the second dielectricspacers 113 a, 113 b are formed over the sidewalls of the stack-gatestructure along the word lines. The second dielectric spacer 113 a, 113b is preferably made of silicon-oxides deposited by LPCVD and the spacerwidth is preferably between 200 Å and 1500 Å.

[0037]FIG. 4F shows that the planarized fourth conductive layers 114 aare formed over the common-source/drain diffusion regions and betweenthe second dielectric spacers 113 a and 113 b. The planarized fourthconductive layers 114 a are formed by first depositing a thick fourthconductive layer 114 to fill up the gaps between the second dielectricspacers 113 a, 113 b and then planarizing the thick fourth conductivelayer 114 using CMP with the Interlayer dielectric layer 109 a as apolishing stop. The thick fourth conductive layer 114 is preferably madeof doped polycrystalline-silicon as deposited by LPCVD. A high-doseion-implantation is performed to heavily dope the planarized fourthconductive layers 114 a and the dopant impurities are preferablyphosphorous. Subsequently, a rapid thermal annealing (RTA) is performedto activate and redistribute the implanted impurities.

[0038]FIG. 4G shows that the patterned photoresist PR5 are formed overthe common-drain lines and the part of the interlayer dielectric layers109 a, and then the planarized fourth conductive layers 114 a over thecommon-source lines are etched back to a level approximately equal tothe bottom level of the control-gate layer 108 a to form a thinnerfourth conductive layers 114 b over the common-source lines.

[0039]FIG. 4H shows that the patterned photoresist PR5 are stripped anda well-known self-aligned silicidation process is performed to form asilicide layer 115 a over the planarized fourth conductive layers 114 aand a silicide layer 115 b over the thinner fourth conductive layers 114b. The suicide layer 115 a, 115 b is preferably made of refractory-metalsilicide such as TiSi₂, CoSi₂, TaSi₂, MoSi₂, NiSi₂ or PtSi₂ etc.

[0040]FIG. 4I shows that a first tick-oxide film 116 is deposited tofill up the gaps over the common-source lines as shown in FIG. 4H andCMP is then performed to planarize the first thick-oxide film 116 a byusing the interlayer dielectric layers 109 a as a polishing stop. Ametal layer 117 is deposited over the whole structure and a thirdmasking dielectric layer 118 is then deposited over the metal layer 117.The patterned photoresist PR6 (not shown) are formed over the thirdmasking dielectric layer 118 to define the bit lines. In order toeliminate the misalignment between the bit lines and the active-regionlines, the third dielectric spacers 119 a are formed over the sidewallsof the patterned third masking dielectric layer 118 a as shown in FIG.2D through FIG. 2F, the metal layer 117, the silicide layer 115 a andthe planarized fourth conductive layer 114 a over the common-drain linesare etched, as will be discussed later. The first thick-oxide layer 116is preferably deposited by CVD or high-density plasma CVD and can bephosphorous-silicate glass (PSG) or pure oxide. The metal layer 117 canbe a tungsten-silicide layer, tungsten, aluminum, or copper formed overa barrier-metal layer such as titanium-nitride (TiN) or tantalum-nitride(TaN). The third masking dielectric layer 118 is preferably made ofsilicon-nitrides, silicon-oxynitrides, or silicon-oxides, as depositedby LPCVD. Similarly, the third dielectric spacer 119 a is preferablymade of silicon-nitrides, silicon-oxynitrides or silicon-oxides.

[0041] Referring now to FIG. 2D through FIG. 2F, there are shown variouscross-sectional views as indicated in FIG. 4I. FIG. 2D shows across-sectional view along the common-source line as indicated by B-B′in FIG. 4I. It is clearly seen that the tinner fourth conductive layer114 b capped with a silicide layer 115 b is formed over a flat bedformed by the common-source diffusion regions 112 b and the etchedfield-oxides 104 c. Therefore, the common-source bus line with lowerbus-line resistance, lower bus-line capacitance and lower pn junctioncurrent leakage can be easily obtained by the present invention.Moreover, the contact integrity for shallow source junction can be muchimproved by using polysilicon contact. As shown in FIG. 2D, the bit-line117 a is defined by a patterned third masking dielectric layer 118 a andtwo third dielectric spacers 119 a, the width of the bit line is widerthan a minimum-feature-size F and the misalignment between the bit lineand the active region can be reduced. FIG. 2E shows a cross-sectionalview along a word line as indicated by C-C′ in FIG. 4I. It is clearlyseen that the integrated floating-gate layer including a majorfloating-gate layer 102 b and two extended floating-gate layers 105 dmay largely increase the coupling ratio of the floating-gate. FIG. 2Fshows a cross-sectional view along the common-drain line as indicated byD-D′ in FIG. 4I. It is clearly visualized that the third dielectricspacers 119 a may prevent the misalignment of the bit-line connectionbetween the common-drain diffusion region 112 a and the planarizedfourth conductive layer 114 a, and the etching of the planarized fourthconductive layers 114 a will be automatically stopped by thefield-oxides 104 b. It should be noted that the gaps between the thirddielectric spacers 119 a can be further filled with a thick CVD oxidefilm and CMP is performed to planarize the CVD-oxide film using thethird masking dielectric layer 118 a as a polishing stop.

[0042] While the present invention has been particularly shown anddescribed with a reference to the present examples and embodiments asconsidered as illustrative and not restrictive. Moreover, the presentinvention is not to be limited to the details given herein, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departure from the true spirit and scope ofthe present invention.

What is claimed is:
 1. A contactless NOR-type memory array, comprising:a semiconductor substrate of a first conductivity type; a plurality ofparallel isolation regions and a plurality of active regions beingformed alternately on said semiconductor substrate, wherein a raisedfield-oxide film is formed on each of the plurality of parallelisolation regions and a thin tunneling dielectric layer is formed overeach of the plurality of active regions; a plurality of word lines beingformed alternately on said semiconductor substrate and transversely tothe plurality of parallel isolation regions, wherein each of theplurality of word lines comprises an elongated control-gate layer beingsandwiched between an interlayer dielectric layer formed on the top andan intergate dielectric layer formed at the bottom, and a plurality ofintegrated floating-gate layer being formed beneath said intergatedielectric layer; wherein each of the plurality of integratedfloating-gate layers comprises a major floating-gate layer being formedon said thin tunneling-dielectric layer and two extended floating-gatelayers being formed separately on a portion of each of two nearby raisedfield-oxide films; a plurality of common-source diffusion regions beingformed in said semiconductor substrate of the plurality of activeregions along a plurality of common-source lines, wherein each of theplurality of common-source lines is situated in every two of said wordlines and between a pair of said word lines; a plurality of common-draindiffusion regions being formed in said semiconductor substrate of theplurality of active regions along a plurality of common-drain lines,wherein each of the plurality of common-drain lines is situated betweena pair of said word lines formed between a pair of said common-sourcelines; a plurality of flat beds being located in the plurality ofcommon-source lines, wherein said raised field-oxide films along each ofthe plurality of common-source lines are etched and each of theplurality of flat beds is formed alternately by the plurality ofcommon-source diffusion regions and said etched raised field-oxidefilms; a plurality of first dielectric spacers being formed over thesidewalls of the plurality of word lines and on a portion of each of theplurality of flat beds, and a plurality of second dielectric spacersbeing formed over the sidewalls of the plurality of word lines and on aportion of each of the plurality of common-drain diffusion regions and aportion of said raised field-oxide films along the plurality ofcommon-drain lines; a plurality of silicided common-source conductivelayers being situated on the plurality of common-source lines, whereineach of the plurality of silicided common-source conductive layers isformed over said flat bed between a pair of said first dielectricspacers with a second thick-oxide layer formed on the top; a pluralityof silicided common-drain conductive islands being situated on theplurality of common-drain lines, wherein each of the plurality ofsilicided common-drain conductive islands is formed between a pair ofsaid second dielectric spacers and on a portion of each of the pluralityof common-drain diffusion regions and a portion of said raisedfield-oxide films along each of the plurality of common-drain lines; anda plurality of bit lines being formed above the plurality of activeregions and transversely to the plurality of word lines, wherein each ofthe plurality of bit lines is formed over a flat surface formedalternately by said second thick-oxide layer, said interlayer dielectriclayer, and said silicided common-drain conductive island having a hardmasking layer formed on a metal layer to simultaneously pattern and formsaid metal layer and said silicided common-drain conductive islandsalong each of the plurality of bit lines.
 2. The contactless NOR-typememory array according to claim 1, wherein the plurality of parallelisolation regions are formed by using shallow-trench-isolation (STI)techniques.
 3. The contactless NOR-type memory array according to claim1, wherein the plurality of parallel isolation regions are formed byusing local-oxidation of silicon (LOCOS) techniques.
 4. The contactlessNOR-type memory array according to claim 1, wherein said elongatedcontrol-gate layer is preferably a composite conductive layer having arefractory-metal silicide layer formed over a dopedpolycrystalline-silicon layer.
 5. The contactless NOR-type memory arrayaccording to claim 1, wherein said interlayer dielectric layer ispreferably a compositive dielectric layer having a cappingsilicon-nitride layer formed on a first thick-oxide layer, asilicon-oxynitride layer or an insulator layer of low dielectricconstant.
 6. The contackless NOR-type memory array according to claim 1,wherein said intergate dielectric layer is preferably a compositedielectric layer having a n oxide-nitride-oxide structure or anitride-oxide structure.
 7. The contactless NOR-type memory arrayaccording to claim 1, wherein said integrated floating-gate layer ispreferably made of doped polycrystalline-silicon or dopedamorphous-silicon.
 8. The contactless NOR-type memory array according toclaim 1, wherein said first dielectric spacer and said second dielectricspacer are preferably made of silicon-oxides, silicon-oxynitrides,silicon-nitrides, or dielectric materials of low dielectric constant. 9.The contactless NOR-type memory array according to claim 1, wherein saidsilicided common-source conductive layer and said silicided common-drainconductive island are preferably a refractory-metal silicide layerformed on a doped polycrystalline-silicon or doped amorphous-siliconlayer,
 10. The contactless NOR-type memory array according to claim 1,wherein said metal layer is preferably aluminum (Al), copper (Cu),tungsten (W), or tungsten-silicide (WSi₂) on a barrier-metal layer suchas TiN or TaN.
 11. The contactless NOR-type memory array according toclaim 1, wherein said hard masking layer comprises a masking dielectriclayer and its two sidewall dielectric spacers and is preferably made ofsilicon-nitrides or silicon-oxides or silicon-oxynitrides.
 12. Thecontactless NOR-type memory array according to claim 1, wherein saidcommon-source diffusion region is preferably a double-diffused structurehaving a heavily-doped source diffusion region of said secondconductivity type formed within a lightly-doped source diffusion regionof said second conductivity type and said common-drain diffusion regionis preferably a heavily-doped drain diffusion region of said secondconductivity type.
 13. The contactless NOR-type memory array accordingto claim 1, wherein said common-source diffusion region is preferably adouble-diffused structure having a heavily-doped source diffusion regionof said second conductivity type formed within a lightly-doped sourcediffusion region of said second conductivity type and said common-draindiffusion region is preferably a double-diffused structure having aheavily-doped diffusion region of said second conductivity type formedwithin a lightly-doped diffusion region of said first conductivity type.14. The contactless NOR-type memory array according to claim 1, whereinsaid common-source diffusion region and said common-drain diffusionregion are preferably a double-diffused structure having a heavily-dopedsource/drain diffusion region of said second conductivity type formedwithin a lightly-doped source/drain diffusion region of said secondconductivity type.
 15. A contactless NOR-type memory array, comprising:a semiconductor substrate of a first conductivity type; a plurality ofparallel shallow-trench-isolation (STI) regions and a plurality ofactive regions being formed alternately on said semiconductor substrate,wherein a raised field-oxide film is formed on each of the plurality ofparallel STI regions and a thin tunneling-dielectric layer is formedover each of the plurality of active regions; a plurality of word linesbeing formed alternately on said semiconductor substrate andtransversely to the plurality of parallel STI regions, wherein each ofthe plurality of word lines comprises an elongated polycide-gate layerbeing sandwiched between a capping silicon-nitride layer over a firstthick-oxide layer formed on the top and an intergate dielectric layerformed at the bottom, and a plurality of integrated floating-gate layersbeing formed beneath said intergate dielectric layer; wherein each ofthe plurality of integrated floating-gate layers comprises a majorfloating-gate layer formed on said thin tunneling-dielectric layer andtwo extended floating-gate layers being formed separately on a portionof each of two nearby raised field-oxide films; a plurality ofcommon-source diffusion regions being formed in said semiconductorsubstrate of the plurality of active regions along a plurality ofcommon-source lines, wherein each of the plurality of common-sourcelines is situated in every two of said word lines and between a pair ofsaid word lines and each of the plurality of common-source diffusionregions comprises a heavily-doped diffusion region of a secondconductivity type formed within a lightly-doped diffusion region of saidsecond conductivity type; a plurality of common-drain diffusion regionsbeing formed in said semiconductor substrate of the plurality of activeregions along a plurality of common-drain lines, wherein each of theplurality of common-drain lines is situated between a pair of said wordlines formed between a pair of said common-source lines and each of theplurality of common-drain diffusion regions comprises a heavily-dopeddiffusion region of said second conductivity type; a plurality of flatbeds being located in the plurality of common-source lines, wherein saidraised field-oxide films along each of the plurality of common-sourcelines are etched and each of the plurality of flat beds is formedalternately by the plurality of common-source diffusion regions and saidetched raised field-oxide films; a plurality of first dielectric spacersbeing formed over the sidewalls of the plurality of word lines and on aportion of each of the plurality of flat beds, and a plurality of seconddielectric spacers being formed over the sidewalls of the plurality ofword lines and on a portion each of the plurality of common-draindiffusion regions and a portion of said raised field-oxide films alongeach of the plurality of common-drain lines; a plurality ofheavily-doped polycrystalline-silicon layer capped with a first silicidelayer being situated on the plurality of common-source lines, whereineach of the plurality of heavily-doped polycrystalline-silicon layers isformed over said flat bed between a pair of said first dielectricspacers having a second thick-oxide layer formed on the top of saidfirst silicide layer; a plurality of heavily-dopedpolycrystalline-silicon islands capped with a second silicide layerbeing situated on the plurality of common-drain lines, wherein each ofthe plurality of heavily-doped polycrystalline-silicon islands is formedbetween a pair of said second dielectric spacers and on a portion ofeach of the plurality of common-drain diffusion regions and a portion ofsaid raised field-oxide films formed nearby; and a plurality of bitlines being formed above the plurality of active regions andtransversely to the plurality of word lines having each of the pluralityof bit lines formed over a flat surface formed alternately by saidsecond thick-oxide layer, said capping silicon-nitride layer, and saidsecond silicide layer, wherein each of the plurality of bit linescomprises a hard masking layer being formed on a metal layer and saidhard masking layer including a masking dielectric layer and its twosidewall dielectric spacers is used to simultaneously pattern and formsaid metal layer and said second silicide layer, and said heavily-dopedpolycrystalline-silicon islands along each of the plurality of bitlines.
 16. A contactless NOR-type memory array, comprising: asemiconductor substrate of a first conductivity type; a plurality ofparallel shallow-trench-isolation (STI) regions and a plurality ofactive regions being formed alternately on said semiconductor substrate,wherein a raised field-oxide film is formed on each of the plurality ofparallel STI regions and a thin tunneling-dielectric layer is formedover each of the plurality of active regions; a plurality of word linesbeing formed alternately on said semiconductor substrate andtransversely to the plurality of parallel STI lines, wherein each of theplurality of word lines comprises an elongated polycide-gate layer beingsandwiched between a capping silicon-nitride layer over a firstthick-oxide layer formed on the top and an intergate dielectric layerformed at the bottom, and a plurality of integrated floating-gate layersbeing formed beneath said intergate dielectric layer; wherein each ofthe plurality of integrated floating-gate layers comprises a majorfloating-gate layer formed on said thin tunneling-dielectric layer andtwo extended floating-gate layers being formed separately on a portionof each of two nearby raised field-oxide films; a plurality ofcommon-source diffusion regions being formed in said semiconductorsubstrate of the plurality of active regions along a plurality ofcommon-source lines, wherein each of the plurality of common-sourcelines is situated between a pair of said word lines formed between apair of said common-source lines and each of the plurality ofcommon-source diffusion regions comprises a heavily-doped diffusionregion of a second conductivity type formed within a lightly-dopeddiffusion region of said second conductivity type; a plurality ofcommon-drain diffusion regions being formed along the plurality ofcommon-drain lines, wherein each of the plurality of common-draindiffusion regions comprises a heavily-doped diffusion region of saidsecond conductivity type formed within a lightly-doped diffusion regionof said first conductivity type; a plurality of flat beds being locatedin the plurality of common-source lines, wherein said raised field-oxidefilms along each of the plurality of common-source lines are etched andeach of the plurality of flat beds is formed alternately by theplurality of common-source diffusion regions and said etched raisedfield-oxide films; a plurality of first dielectric spacers being formedover the sidewalls of the plurality of word lines and on a portion ofeach of the plurality of flat beds, and a plurality of second dielectricspacers being formed over the sidewalls of the plurality of word linesand on a portion of each of the plurality of common-drain diffusionregions and a portion said raised field-oxide films along each of theplurality of common-drain lines; a plurality of heavily-dopedpolycrystalline-silicon layers capped with a first silicide layer beingsituated on the plurality of common-source lines, wherein each of theplurality of heavily-doped polycrystalline-silicon layers is formed oversaid flat bed between a pair of said first dielectric spacers having asecond thick-oxide layer formed on the top of said first silicide layer;a plurality of heavily-doped polycrystalline-silicon islands capped witha second silicide layer being situated on the plurality of common-drainlines, wherein each of the plurality of heavily-dopedpolycrystalline-silicon islands is formed between a pair of said seconddielectric spacers and on a portion of each of the plurality ofcommon-drain diffusion regions and a portion of said raised field-oxidefilms formed nearby; and a plurality of bit lines being formed above theplurality of active regions and transversely to the plurality of wordlines having each of the plurality of bit lines formed over a flatsurface formed alternately by said second thick-oxide layer over saidfirst silicide layer, said capping silicon-nitride layer over said firstthick-oxide layer over said elongated polycide-gate layer, and saidsecond silicide layer over said heavily-doped polycrystalline-siliconislands, wherein each of the plurality of bit lines comprises a hardmasking layer being formed on a metal layer and said hard masking layerincluding a masking dielectric layer and its two sidewall dielectricspacers is used to simultaneously pattern and form said metal layer,said second silicide layer, and said heavily-dopedpolycrystalline-silicon islands along each of the plurality of bitlines.
 17. The contactless NOR-type memory array according to claim 15or claim 16, wherein said first dielectric spacer and said seconddielectric spacer are preferably made of silicon-oxides,silicon-oxynitrides, silicon-nitrides or dielectric materials of lowdielectric constant.
 18. The contactless NOR-type memory array accordingto claim 15 or claim 16, wherein said first silicide layer and saidsecond silicide layer are preferably made of refractory-metal silicidessuch as TiSi₂, CoSi₂, TaSi₂, MoSi₂, NiSi₂, WSi₂ or PtSi₂ etc.
 19. Thecontacless NOR-type memory array according to claim 15 or claim 16,wherein said metal layer is preferably consisting of aluminum (Al),copper (Cu), tungsten (W) or tungsten-silicide (Wsi₂) formed over abarrier-metal layer.
 20. The contactless NOR-type memory array accordingto claim 15 or clam 16, wherein said hard masking layer including amasking dielectric layer and its two sidewall dielectric spacer arepreferably made of silicon-nitrides, silicon-oxynitrides orsilicon-oxides.